The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof. In particular, the invention pertains to a technique effective when adapted to a semiconductor integrated circuit device having an MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate length of next generation not greater than 0.15 xcexcm and is required to have high speed operation.
In a so-called SALICIDE (self-aligned silicide) technique by which a refractory metal silicide layer, for example, a layer of cobalt silicide (CoSi2) or titanium silicide (TiSi2) is formed over the source/drain and gate electrode of MISFET, an increase in a contact resistance is prevented by setting an impurity concentration on the surface of a semiconductor brought into contact with the silicide layer at 1xc3x971020 cmxe2x88x923 or greater.
In FIG. 29, shown is an influence of an impurity concentration in a semiconductor on the contact resistance between a metal and a semiconductor. FIG. 29(a) illustrates the contact resistance with a semiconductor of an n conductivity type, while FIG. 29(b) illustrates the contact resistance with a semiconductor of a p conductivity type. The contact resistance between the metal and the semiconductor was calculated from the following equation (1):
Exp (A "PHgr"/SQRT (N))xe2x80x83xe2x80x83Equation (1)
wherein, "PHgr" stands for a difference in the work function between the metal and semiconductor, N stands for an impurity concentration in the semiconductor, and A means a proportionality factor. The drawings suggest that the contact resistance shows a drastic increase when the impurity concentration in the semiconductor becomes less than 1xc3x971020 cmxe2x88x923.
The silicide-layer forming technique over source/drain regions which technique has been investigated by the present inventors will next be described simply.
First, an impurity of a relatively low concentration is injected to a substrate by ion implantation from the outside of a gate electrode, whereby extended semiconductor regions (which will hereinafter be called xe2x80x9csource/drain extended regionsxe2x80x9d) constituting a part of source/drain are formed in the substrate at both sides of a gate electrode. After disposal of side wall spacers on the side walls of the gate electrode, an impurity of a relatively high concentration is injected to the substrate by ion implantation from the outside of these side wall spacers, whereby diffused semiconductor regions (which will hereinafter be called xe2x80x9csource/drain diffused regionsxe2x80x9d) constituting another portion of source/drain and having a surface concentration of 1xc3x971020 cmxe2x88x923 or greater are formed in the substrate at both sides of the gate electrode. On the surface of these source/drain diffused regions, a silicide layer is formed in self alignment.
In a semiconductor device of the generation wherein the gate length is 0.2 xcexcm or greater, the junction depth of the source/drain diffused regions is about 0.2 xcexcm and width in the lateral direction is about 0.1 xcexcm, while the thickness of the silicide layer, more specifically, that of a CoSi2 film is about 0.04 xcexcm and that of a TiSi2 film is about 0.07 xcexcm, which is set thinner than the lateral width of the source/drain diffused regions.
In a semiconductor device of the generation having a gate length not greater than 0.15 xcexcm or less, however, the junction depth of the source/drain regions and the width in the lateral direction decrease to 0.1 xcexcm or less and 0.05 xcexcm or less, respectively. It has been revealed by the present inventors that in such a device, the width in the lateral direction becomes much the same with the thickness of the silicide layer, causing an unknown problem that the silicide layer is inevitably brought into contact with the source/drain extended regions.
Since the impurity concentration in the source/drain extended regions is set at a relatively low level in order to reduce an occurrence ratio of hot carriers, the contact resistance increases by the contact of the silicide layer with the source/drain extended regions, leading to lowering of the on-state current of MISFET. In particular, when side wall spacers are each formed of a silicon oxide film, they are etched during a cleaning step of a substrate with hydrofluoric acid (HF) and the silicide layer tends to be brought into contact with the source/drain extended regions, leading to marked lowering of the on-state current of MISFET.
In an MISFET having a so-called build-up source/drain structure which is obtained by forming side wall spacers on the side walls of a gate electrode, and then allowing a silicon (Si) layer or a germanium(GE)-containing Si layer to selectively grow on a substrate, a facet appears at the end portion of the side wall spacers (which will hereinafter be called xe2x80x9cspacer end portionxe2x80x9d), causing a decrease in the thickness of the Si layer at the spacer end portion. Moreover, in this MISFET having a build-up source/drain structure, the silicide layer is formed thicker than the silicide layer of an MISFET having an ordinary source/drain structure to reduce a sheet resistance so that an encroachment amount in the lateral direction at the spacer end portion becomes large, tending to cause a problem that the silicide layer is brought into contact with the source/drain extended regions.
An object of the present invention is to provide a technique capable of realizing high-speed operation of MISFET of the generation having a gate length of 0.15 xcexcm or less.
The above-described object and another object, and novel features of the present invention will be apparent from both the description therein and accompanied drawings.
Of the inventions to be disclosed by the present application, typical ones will next be summarized briefly.
(1) A semiconductor integrated circuit device according to the present invention comprises an MISFET equipped with source/drain extended regions formed by introducing n-type impurities into a substrate with a gate electrode as a mask, source/drain diffused regions formed by introducing n-type impurities into the substrate with the gate electrode and side wall spacers, which have been formed on the side surfaces (walls) of the gate electrode, as masks and a cobalt silicide layer on the surface of the source/drain diffused regions, wherein
the junction depth of the source/drain extended regions is smaller than that of the source/drain diffused regions, an n-type semiconductor region formed by introducing n-type impurities into the substrate with the gate electrode and side wall spacers as masks, lies between the source/drain extended regions and the source/drain diffused regions, a portion or the whole portion of the end portion of the cobalt silicide layer is in contact with the n-type semiconductor region, and the impurity concentration in the n-type semiconductor region is higher than that of the source/drain extended regions.
(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: forming over a substrate a gate electrode made of a silicon film, implanting ions of a first n-type impurity into the substrate with the gate electrode as a mask, thereby forming source/drain extended regions, forming side wall spacers on the side walls of the gate electrode, implanting ions of a second n-type impurity into the substrate with the gate electrode and side wall spacers as masks, thereby forming source/drain diffused regions, cleaning the substrate, and after deposition of a cobalt film over the substrate, heat treating the substrate, thereby forming a cobalt silicide layer over the surface of the source/drain diffused regions, which further comprises, prior to the formation of the side wall spacers, of the step of:
implanting, with the gate electrode and side wall spacers as masks, ions of a third n-type impurity into the substrate obliquely at a predetermined inclination relative to the normal line of the substrate, thereby forming an n-type semiconductor region.
By the above-described means, the n-type semiconductor region is formed between the source/drain extended regions and source/drain diffused regions of MISFET, a portion or the whole portion of the end portion of the silicide layer formed in the substrate is surrounded by the n-type semiconductor region, and the impurity concentration of the n-type semiconductor region at a portion to be brought into contact with the silicide layer is made relatively high, for example, about 1xc3x971020 cmxe2x88x923. This structure makes it possible to lessen the contact resistance of the silicide layer, leading to relaxation of a voltage drop when the current flows from the silicide layer to the source/drain extended regions.